// module name: regfile
// description:
//   1. two data-out ports
//   2. one data-in port
// author: yangtao2019
// date: 2021.07.11

`timescale 1ns / 1ps

module regfile(
    input clk,
    // Read Register1
    input [4:0] read_addr1,
    output [63:0] read_data1,
    // Read Register2
    input [4:0] read_addr2,
    output [63:0] read_data2,
    // Write Register
    input write_en,
    input [4:0] write_addr,
    input [63:0] write_data
);

    // 32 regs, each 4-Byte wided
    reg [63:0] regs[31:0];
    //wire [31:0] waddr_ena, raddr1_ena, raddr2_ena;

    // data-out1: immediately
    assign read_data1 = (read_addr1==64'b0) ? 1'b0 : regs[read_addr1];
    // means reg1 always keeps low 

    // data-out2: immediately
    assign read_data2 = (read_addr2==64'b0) ? 1'b0 : regs[read_addr2];

    // data-in: takes 1-cycle 
    always @ (posedge clk) begin
        if (write_en)
            regs[write_addr] = write_data;
    end

endmodule

